EMC-F3UF
eMMC 5.1
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eMMC encloses the TLC NAND and eMMC controller inside as one JEDEC standard package, providing a standard interface to the host.
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The eMMC controller directly manages NAND flash, including ECC, wear-leveling, IOPS optimization and read sensing.
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Product Specifications
| Series Name | EMC-F3UF | ||||
|---|---|---|---|---|---|
| Interface | eMMC 5.1 | ||||
| Capacity Coverage | 8GB~256GB | ||||
| Capacity | |||||
| 3D TLC | 32GB~256GB | ||||
| 3D pSLC | 8GB~64GB | ||||
| Performance Overview | Seq. R : 315 MB/s ; Seq. W : 240MB/s | ||||
| Performance | |||||
| 3D TLC | Seq. R : 315 MB/s ; Seq. W : 240MB/s | ||||
| 3D pSLC | Seq. R : 315 MB/s ; Seq. W : 240MB/s | ||||
| Standard Operating Temperature | -25J ~ 85J | ||||
| Extended Operating Temperature | -40J ~ 85J | ||||
| Dimension LxWxH (mm) | 153 balls : 11.5mm x 13mm x 1mm | ||||
| Technology | ##Write Protect ? | ||||
| Data Sheet |  |
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